1. Field of the Invention
The present invention generally relates to a method for manufacturing semiconductor devices, and more specifically to a method for manufacturing a semiconductor device including a control electrode of a field effect transistor, wires formed on a semiconductor substrate and the like.
2. Description of the Prior Art
FIG. 1 is a block diagram showing one example of a typical DRAM structure, and FIG. 2 is an equivalent circuit diagram of one memory cell arranged in the memory cell array of FIG. 1.
The structure will be briefly described with reference to the figures. A plurality of word lines 110 and a plurality of bit lines are arranged in the memory cell array 101 and memory cells each comprising a MOS transistor 108 and a capacitor 109 are connected to the intersections. The selection of the memory cell is effected based on a word line and a bit line selected by a X address buffer.decoder 102 and a Y address buffer.decoder 103, respectively. The instruction for writing/reading data to and from the memory cell is effected by a signal (R/W) applied to a R/W control circuit 104. In reading, the data stored in the selected memory cell is detected by a sense amplifier 105, amplified therein, and is outputted externally as an output data (Dout) through a data output buffer 106.
FIG. 3 is a plan view showing a portion of the memory cell array shown in FIG. 1 and FIG. 4 is a cross sectional view taken along the line IV--IV of FIG. 3. The structure will be described in the following with reference to the figures.
A region for isolating devices is formed on a semiconductor substrate 1 by an ion diffused layer 2 having the same conductivity type as the substrate 1 and a thick oxide film 3. An ion diffused layer 4 having the conductivity type opposite to that of the semiconductor substrate 1 for forming a direct contact, a storage node 5 formed of a material of polycrystalline silicon (polysilicon) system for storing charges and a cell plate electrode 6 formed of a material of polysilicon system form a capacitor region.
A transfer gate electrode 7 formed of a single layer of polysilicon, two layers of polysilicon and a metal having high melting point or a single layer of a metal having high melting point, and an ion diffused layer 8 (8a, 8b, 8c) having a conductivity type opposite to the semiconductor substrate 1 for forming source/drain regions form a transfer gate transistor region. An interlayer insulating film 14 formed of an oxide film is formed to cover the capacitor region and the transfer gate transistor region. A contact hole 9 is formed in the interlayer insulating film 14 to provide contact with the ion diffused layer 8b.
A bit line 10 formed of two layers of polysilicon and a metal having high melting point or of a metal having high melting point is formed on the interlayer insulating film 14 so as to be connected with the ion diffused layer 8b through the contact hole 9. A thin insulating film 11 having multilayer structure of an oxide film and a nitride film is formed between the storage node 5 and the cell plate electrode 6, and an insulating film 12 formed of an oxide film is formed below the transfer gate electrode 7.
FIG. 5 shows a cross sectional structure of a field effect transistor having LDD (Lightly Doped Drain/Source) structure.
The structure will be described in the following with reference to the figure. An active region is formed on a semiconductor substrate 21 by ion diffused layers 23a and 23b having the same conductivity type as the substrate and by thick oxide films 22a and 22b. Impurity regions 24a and 24b having the opposite conductivity type is formed on a main surface of the semiconductor substrate in the active region. Impurity regions 25a and 25b having high impurity concentration are connected respectively to the impurity regions 24a and 24b, thereby forming the LDD structure. A gate electrode 28 is formed on the main surface of the semiconductor substrate between the impurity regions 25a and 25b, with a gate oxide film 27 interposed therebetween. An interlayer insulating film 26 is formed on the entire surface of the active region to cover the gate electrode 28. Metal interconnections 30, 29 formed on the interlayer insulating film 26 are respectively connected to the impurity region 24b and the gate electrode 28 through contact holes 31, 32 formed on the interlayer insulating film 26.
The above described LDD structure has been developed to prevent the disadvantages of short channel effect in the transistor incidental to the recent high integration of the semiconductor devices. The manufacturing method thereof has been more complicated.
As the wafer size has become larger, and the devices have become smaller and come to be implemented in higher integration, various problems, which were not so important, have become serious. One of these problems is a thermal influence caused by the heat treatment in the manufacturing process, and therefore it is desired to carry out the manufacturing process in lower temperature. In addition, it is strongly desired to improve the speed of operation of the devices, and the electrodes and wires are required to have lower resistance in order to attain the high speed operation. A new manufacturing process and technique as well as the improvement and development of the device structure should be established sooner.
FIGS. 6A to 6E are schematic cross sectional views showing the steps of manufacturing a conventional field effect transistor. The manufacturing method will be described with reference to the figures.
First, a thin silicon oxide film 202 is formed on a main surface of a P type semiconductor substrate 201 by thermal oxidation method and the like, and thereafter, a polycrystalline silicon film 204 is formed by CVD method and the like. After the resistance of the polycrystalline silicon film 204 is lowered by phosphorus treatment or the like, a silicide film 205, for example, a tungsten silicide (WSi.sub.2) film, is formed by sputtering and the like (FIG. 6A).
Thereafter, the said silicide film 205 and the polycrystalline silicon film 204 are patterned by photolithography, and a gate electrode 203 having polyside structure is formed on the gate oxide film 202 (FIG. 6B).
Next, ion implantation 206 of for example arsenic ions is carried out under a prescribed implantation condition from the side of the main surface of the said substrate 201, whereby an N type impurity region 207 is formed on a main surface of the said substrate 201 on both sides of the said gate electrode 203, with the gate electrode serving as a mask (FIG. 6C). Thereafter, heat treatment is carried out at about 900.degree. C. for 60 minutes, for example, whereby the said N type impurity region 207 becomes the source region 208a and a drain region 208b of N type diffused region. A portion between these two regions serves as a channel portion, thereby forming a MOS transistor.
Thereafter, an insulating film 209 is formed by the CVD method and the like on the said substrate 201 to cover the said gate electrode 203, and thereafter, a reflow film 210, for example BPSG (boron.phosphorus.silicate glass) is formed thereon (FIG. 6D). In this state, the upper surface becomes concave on the upper portion of the said gate electrode 203 to have a steep step. The step portion affects wires formed thereon in the later steps as shown in FIG. 5 such as disconnection and the like, so that some measures should be taken to solve the problem of the step portion.
Thereafter, reflow oxidation is carried out in wet atmosphere at about 900.degree. C. for 30 minutes, for example, whereby the said reflow film 210 is made a flat film 210a with the upper surface made smooth (FIG. 6E). Although not shown, patterning by photolithography is carried out to form contact holes in the said flat film 210a and the insulating film 209. Thereafter, interconnection film, for example an aluminum film is formed on the entire surface and patterning by photolithography is carried out. Consequently, upper layer interconnections formed of aluminum interconnections is formed on the said flat film 210a, the interconnection connected to the said gate electrode 203 and the like through the contact holes (see FIG. 5).
The said semiconductor device is obtained through the above described manufacturing process. The following phenomenon occurs in the manufacturing steps. Namely, in the first heat treatment after the ion implantation 206, an oxidation reaction occurs to generate an oxide film on a main surface of the said gate electrode 203. More specifically, the said gate electrode 203 is directly exposed to the heat treatment space, and an oxide film is generated on the upper layer portion of the said gate electrode 203 by the reaction with the oxygen in the space. If the said silicide film 205 is formed of tungsten silicide, the oxide film formed on a main surface of the said gate electrode 203, namely, on the main surface of the said silicide film 205, is an oxide film or a silicon oxide film such as tungsten dioxide (WO.sub.2), tungsten trioxide (WO.sub.3), or the like. On this occasion, the said silicide film 205 is rich in oxygen being exposed to the heat treatment space. On the contrary, the polycrystalline silicon film 204 which is the source of silicon is under the said silicide film 205. Therefore, the growth of the said silicon oxide film is rate-determined by the amount of silicon supplied through the said silicide film 205 by thermal diffusion.
During the oxidation process, the crystallization of the silicide takes place in the said silicide film 205. The said silicide begins to crystallize gradually when a prescribed temperature is exceeded, and the larger the diameter of the crystal grain becomes, the larger the grain boundary becomes.
Meanwhile, the said generated oxide film has a porous structure, so that it allows diffusing oxygen to pass therethrough. The said silicide film 205 has a large grain boundary, so that it allows the passage of silicon. Namely, these films do not prevent the gradual generation of the said oxide film.
In the second heat treatment in reflow oxidation, an oxidation reaction occurs in which a silicon oxide film 211 is further formed on the generated oxide film on the main surface of the said silicide film 205. More specifically, silicon is thermally diffused through the said silicide film 205 to the upper layer side from the said polycrystalline silicon film 204. Oxygen is thermally diffused through the reflow film 210 and through the insulating film 209 from the heat treatment space to the side of the said gate electrode 203. When the silicon and the oxygen reach the said generated oxide film, they are coupled to each other to generate a silicon oxide film 211. On this occasion, the said silicide film 205 is rich in silicon because much silicon is supplied from the said polycrystalline silicon film 204 therebelow. On the contrary, the oxygen should be thermally diffused through the insulating film 209 and the reflow oxide film 10 on the said generated oxide film. Therefore, the growth of the said silicon oxide film 211 is rate-determined by the amount of supplied oxygen. Since the said silicon oxide film 211 has a porous structure, it allows the passage of silicon, so that it does not prevent the gradual generation of the said silicon oxide film 211.
Although the above described phenomenon is incidental to the said first and second heat treatment, these heat treatments are essential in the process of manufacturing semiconductor devices. The said first heat treatment is to recover the damage of the impurity region 207 to which prescribed ions are implanted, and to provide a prescribed diffused region. The said second heat treatment is to make flat the said reflow film 210 prior to the formation of the upper layer interconnections so as to make smooth and small the step at the interlayer insulating portion, thereby preventing this connection or short circuit of the said upper layer interconnections at the step portion and enabling processing of high precision.
Since a conventional semiconductor device is manufactured in the above described manner, the gate electrode 203 is subjected to the oxidation reaction through the steps of heat treatment and is affected by the reaction.
More specifically, the oxide film generated on the silicide film 205 of the said gate electrode 203 through the first heat treatment causes degradation of electrical characteristics such as increase of the sheet resistance of the gate, increase of the contact resistance when it is connected to the upper layer, and the like.
The silicon oxide film 211 formed in the second heat treatment grows as the processing time passes and becomes thick. On the contrary, the silicon in the polycrystalline silicon film 204 which is the source of silicon supply for generating the said silicon oxide film 211 gradually decreases. When the said second heat treatment is completed, the said gate electrode 203 has its main surface bent in a concave shape as shown in FIG. 6E. If this bent grow worse, the degradation of the shape possibly occurs, such as the separation of the said silicide film 205 and the polycrystalline silicon film 204 at the junction surface. As a result, the degradation of the characteristics of the transistor such as fluctuation of the threshold voltage, decrease of the gate breakdown voltage and so on possibly occurs.
As described above, either of the heat treatments cause degradation of the electric characteristics. Especially, the influence of the degradation over the shape is serious, considerably lowering the reliability.